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4 Channel 500MSPS DDS with 10-bit DACs
Preliminary Technical Data
FEATURES
Four synchronized DDS channels @500 MSPS Independent frequency / phase / amplitude control between all channels Matched latencies for Freq, Phase, and Amplitude changes Excellent channel to channel isolation Frequency sweeping capability Up to 16 levels of modulation (pin selectable) Individually programmable DAC full scale currents Four integrated 10-bit D/A converters(DACs) 32-bit frequency tuning resolution 14-bit phase offset resolution 10-bit output amplitude scaling resolution Serial I/O Port(SPI) with enhanced data throughput
AD9959
Software/Hardware controlled power-down Dual supply operation (1.8 V DDS core / 3.3 V serial I/O) Built-in synchronization for multiple devices Selectable REF_CLK multipier(PLL) 4x to 20x (bypassable) Selectable REF_CLK crystal operation 56 pin LFCSP package APPLICATIONS Agile L.O. frequency synthesis Phased array radar / sonar Instrumentation Synchronized clocking RF source for AOTF
FUNCTIONAL BLOCK DIAGRAM
DDS CORE FREQUENCY ACCUMULATOR
32
32
15
COS(X)
10
x x x x
10
10
DAC
IOUT IOUT
DDS CORE FREQUENCY ACCUMULATOR
32
32
15
COS(X)
10
10
DAC
IOUT IOUT
DDS CORE FREQUENCY ACCUMULATOR
32
32
15
COS(X)
10
10
DAC
IOUT IOUT
DDS CORE FREQUENCY ACCUMULATOR RAMP RATE DFTW SYNC_IN SYNC_OUT I/O_UPDATE
32
32
15
COS(X)
10
10
DAC
IOUT IOUT
DAC_RSET
32
8
FTW
32
PHASE OFFSET
14
DIGITAL MULTIPLIER
SCALABLE DAC REF CURRENT
Timing & Control Logic
SYSTEM CLK
CONTROL REGISTERS
PWR_DWN_CTL
MASTER_RESET
SYNC_CLK
/4
SCLK CS
OSC / REF_CLK OSC / REF_CLK
BUFFER / XTAL OSCILLATOR
REF CLOCK MULTIPLIER (PLL) 4x to 20x
M U X
CHANNEL REGISTERS PROFILE REGISTERS
I/O Port Buffer
SDIO_0 SDIO_1 SDIO_2 SDIO_3
1.8V AVDD CLK_MODE_SEL
1.8V DVDD
PPPP SSSS 0123
3.3V DVDD_IO
Figure 1 AD9959 Block Diagram Rev. PrB
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
AD9959 AD9959--SPECIFICATIONS
Preliminary Technical Data
Table 1. Unless otherwise noted, AVDD, DVDD = 1.8 V 5%, DVDD_I/O = 3.3 V 5%, RSET = 1.96 k, External Reference Clock Frequency = 500 MSPS (REF_CLK multiplier bypassed)
Parameter REF CLOCK INPUT CHARACTERISTICS
Frequency Range REF_CLK Multiplier bypassed REF_CLK Multiplier enabled at 4x(min) REF_CLK Multiplier enabled at 20x(max) Internal VCO range w/ REF_CLK multiplier enabled Crystal REF_CLK source mode Input Power Sensitivity Input voltage level Input Capacitance Input Impedance Duty Cycle w/ REF_CLK Multiplier bypassed Duty Cycle w/ REF_CLK Multiplier enabled CLK Mode Select logic 1 Voltage CLK Mode Select logic 0 Voltage 0 25 5 100 20 -15 400 3 1500 50 35 1.25 65 0.6 500 125 25 500 30 3 MHz MHz MHz MHz MHz dBm mV pF ohms % % V V
Min
Typ
Max
Units
Test Conditions/Comments
REF_CLK inputs must be AC coupled due to internal biasing
External 50 ohm termination
Not a 3.3V digital input Not a 3.3V digital input Must be referenced to AVDD
DAC OUTPUT CHARACTERISTICS
Resolution Full Scale Ouput Current Gain Error Output Offset Differential Nonlinearity Integral Nonlinearity Output Capactiance Voltage Compliance Range Channel to Channel Isolation Channel to Channel amplitude matching error 10 10 -10 -0.5 -1 5 AVDD- 0.50 60 2 AVDD + 0.50 10 0.6 0.5 1 Bits mA %FS uA LSB LSB pF V dB %
WIDEBAND SFDR
1-20 MHz Analog Out 20-60 MHz Analog Out 60-100 MHz Analog Out 100-150 MHz Analog Out 150-200 MHz Analog Out -65 -62 -59 -56 -54 dBc dBc dBc dBc dBc
Wideband SFDR defined as DC to Nyquist
NARROWBAND SFDR
1.1 MHz Analog Out (+/- 10kHz) 1.1 MHz Analog Out (+/- 50kHz) 1.1 MHz Analog Out (+/- 250kHz) 1.1 MHz Analog Out (+/- 1MHz) 15.1 MHz Analog Out (+/- 10kHz) 15.1 MHz Analog Out (+/- 50kHz) 15.1 MHz Analog Out (+/- 250kHz) 15.1 MHz Analog Out (+/- 1MHz) 40.1 MHz Analog Out (+/- 10kHz) 40.1 MHz Analog Out (+/- 50kHz) 40.1 MHz Analog Out (+/- 250kHz) 40.1 MHz Analog Out (+/- 1MHz) -90 -88 -86 -85 -90 -87 -85 -83 -90 -87 -84 -82
Rev. PrB | Page 2 of 9
dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc
Preliminary Technical Data
Parameter
75.1 MHz Analog Out (+/- 10kHz) 75.1 MHz Analog Out (+/- 50kHz) 75.1 MHz Analog Out (+/- 250kHz) 75.1 MHz Analog Out (+/- 1MHz) 100.1 MHz Analog Out (+/- 10kHz) 100.1 MHz Analog Out (+/- 50kHz) 100.1 MHz Analog Out (+/- 250kHz) 100.1 MHz Analog Out (+/- 1MHz) 200.1 MHz Analog Out (+/- 10kHz) 200.1 MHz Analog Out (+/- 50kHz) 200.1 MHz Analog Out (+/- 250kHz) 200.1 MHz Analog Out (+/- 1MHz)
AD9959
Min Typ
-87 -85 -83 -82 -87 -85 -83 -81 -87 -85 -83 -81
Max
Units
dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc
Test Conditions/Comments
PHASE NOISE CHARACTERISTICS
Residual Phase Noise @15.1 MHz(Aout) @1kHz offset @10kHz offset @100kHz offset @1MHz offset Residual Phase Noise @ 75.1 MHz(Aout) @1kHz offset @10kHz offset @100kHz offset @1MHz offset Residual Phase Noise @ 200.1 MHz(Aout) @1kHz offset @10kHz offset @100kHz offset @1MHz offset Residual Phase Noise @ 15.1 MHz(Aout) w/ REF CLK multiplier enabled 4x @1kHz offset @10kHz offset @100kHz offset @1MHz offset Residual Phase Noise @ 75.1 MHz(Aout) w/ REF CLK multiplier enabled 4x @1kHz offset @10kHz offset @100kHz offset @1MHz offset Residual Phase Noise @ 200.1 MHz(Aout) w/ REF CLK multiplier enabled 4x @1kHz offset @10kHz offset @100kHz offset @1MHz offset TBD TBD TBD TBD dBc/ Hz dBc/ Hz dBc/ Hz dBc/ Hz TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD dBc/ Hz dBc/ Hz dBc/ Hz dBc/ Hz dBc/ Hz dBc/ Hz dBc/ Hz dBc/ Hz dBc/ Hz dBc/ Hz dBc/ Hz dBc/ Hz
TBD TBD TBD TBD
dBc/ Hz dBc/ Hz dBc/ Hz dBc/ Hz
TBD TBD TBD TBD
dBc/ Hz dBc/ Hz dBc/ Hz dBc/ Hz
SERIAL PORT TIMING CHARACTERISTICS
Maximum Frequency Minimum Clock Pulsewidth Low (tPWL) Minimum Clock Pulsewidth High (tPWH) 200 TBD TBD MHz ns ns
Rev. PrB | Page 3 of 9
AD9959
Maximum Clock Rise/Fall Time Minimum Data Setup Time (tDS) Minimum Data Hold Time TBD TBD TBD
Preliminary Technical Data
ns ns ns
MISC TIMING CHARACTERISTICS
Master_Reset minimum Pulsewidth I/O_Update minimum Pulsewidth Minimum setup time (IO_Update to Sync_CLK) Minimum hold time (IO_Update to Sync_CLK) Minimum setup time (Profile inputs to Sync_CLK) Minimum hold time (Profile inputs to Sync_CLK) TBD 1 TBD 0 TBD 0 Sync CLK Sync CLK ns ns ns ns Pipeline delays for Freq, Phase, Amp changes are programmable to match one another. matched unmatched unmatched unmatched Rising edge to rising edge Rising edge to rising edge
DATA LATENCY (PIPE LINE DELAY)
Matched pipe line of Freq, Phase, Amplitude Frequency word to DAC output Phase Offset word to DAC output Amplitude word to DAC output TBD TBD TBD TBD Sys Clks Sys Clks Sys Clks Sys Clks
CMOS LOGIC INPUTS
VIH VIL Logic 1 Current Logic 0 Current Input Capacitance -12 2 2.8 0.4 TBD TBD TBD TBD TBD TBD TBD TBD mA mA mA mA mA mA 3 2.2 0.6 12 V V uA uA pF V V
CMOS LOGIC OUTPUTS (1 mA Load)
VOH VOL
POWER SUPPLY
Total Power Dissipation- all channels ON, single-tone mode Maximum Power Dissipation- all channels, freq accumulator output multiplier ON Iavdd - All Channels ON, Single tone mode Iavdd - All Ch(s) ON, Freq accum, and output multiplier ON Idvdd - All Ch(s) ON, Single tone mode Idvdd - All Ch(s) ON, Freq accum, and output multiplier ON Idvdd_I/O Power down Mode mW
Rev. PrB | Page 4 of 9
Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Maximum Junction Temperature DVDD_I/O (Pin 49) AVDD, DVDD Digital Input Voltage (DVDD_I/O = 3.3 V) Digital Output Current Storage Temperature Operating Temperature Lead Temperature (10 sec Soldering) JA JC Rating 150C 4V 2V -0.7 V to +4V 5 mA -65C to +150C -40C to +105C 300C 21C/W 2C/W
AD9959
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
CMOS DIGITAL INPUTS
DAC OUPUTS
OSC / REF_CLK INPUTS
AVDD
DVDD_I/O= 3.3V Iout Iout 1.5 k INPUT OUTPUT AVDD REF_CLK
zz
1.5 k REF_CLK AVDD
AVOID OVERDRIVING DIGITAL INPUTS. FORWARD BIASING DIODES MAY COUPLE DIGITAL NOISE ON POWER PINS.
TERMINATE OUTPUTS INTO AVDD. DO NOT EXCEED OUTPUT VOLTAGE COMPLIANCE.
OSC
AMP
OSC
REF_CLK INPUTS ARE INTERNALLY BIASED AND NEED TO BE AC-COUPLED. OSC INPUTS ARE DC COUPLED
Figure 1 Equivalent input and output circuits
Rev. PrB | Page 5 of 9
AD9959
PRODUCT OVERVIEW
The AD9959 consists of four independently programmable DDS channels. The AD9959 features independent frequency, phase, and amplitude control of each channel; this allows for the correction of imbalances due to analog processing such as filtering, amplification, or PCB layout related mismatches. The AD9959 supports frequency sweeping for radar and instrumentation applications. Since all four channels share a common system clock, they are inherently synchronized. If more than four channels are required, synchronizing multiple AD9959s is a simple task. The AD9959 uses advanced DDS technology which provides low power dissipation with high performance. The device incorporates four integrated high speed 10-bit DACs with excellent wideband and narrowband SFDR. Each DDS has a 32bit frequency tuning word, 14-bits of phase offset, and a 10-bit output scale multiplier. Each DAC has it own programmable reference to enable a different full scale current for each channel.
Preliminary Technical Data
Each DDS acts as a high resolution frequency divider with the REF_ CLK as the input and the DAC providing the output. The REF_CLK input source is common to all DDS channels, and can be driven directly, or used in combination with an integrated REF_CLK multiplier (using a PLL) up to a maximum of 500 MSPS. The REF_ CLK multiplication factor is programmable from 4 to 20, in integer steps. The REF_CLK input features an oscillator which supports either a crystal as a source, or may be bypassed. The crystal frequency must be between 20MHz and 30MHz. The crystal can be used with or without the REF_CLK multiplier. The DAC outputs are supply referenced and must be terminated into AVDD by a resistor, or an AVDD center-tapped transformer. The AD9959 comes in a space-saving 56-lead LFCSP package. The DDS core (AVDD and DVDD pins) must be powered by a 1.8V supply. The digital I/O interface (SPI) operates at 3.3V and requires that the pin labeled "DVDD_I/O" (pin 49) be connected to 3.3V. The AD9959 operates over the industrial temperature range of -40C to +85
Rev. PrB | Page 6 of 9
Preliminary Technical Data
PIN CONFIGURATION
AD9959
SYNC _CLK
SD _3 IO
SD _2 IO
SD _1 IO
SD _0 IO
DVDD I/O _
I/O PD _U ATE
DN GD
DD VD
SC LK
DN GD 44
C S
DD VD
56
55
54
53
52
51
50
49
48
47
46
45
SYNC_IN SYNC_OUT MASTER_RESET PWR_DWN_CTL AVDD AGND AVDD CH2_IOUT CH2 _IOUT AGND AVDD AGND CH3_IOUT CH3_IOUT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
43
P3
42 41 40
P2 P1 P0 AVDD AGND AVDD CH1_IOUT CH1_IOUT AGND AVDD AGND AVDD CH0_IOUT CH0_IOUT
AD9959
56-LD LFCSP
39 38 37 36 35 34 33 32 31 30 29
TOP VIEW (Not to Scale)
19 20 21 22 23 24 25 26 27 LO P_FILTER O 28 AG D N
AG D N
AG D N
AVD D
O /R SC EF_C LK
CLK_M DE_SEL O
O /R SC EF_CLK
AG ND
AG ND
AVD D
AVD D
Notes : 1) The exposed EPAD on bottom side of package is an electrical connection and must be soldered to ground. 2) Pin 49 is DVDD_IO and is tied to 3.3V.
D _R E AC S T
Rev. PrB | Page 7 of 9
AVD D
AD9959
Table 3. Pin Function Descriptions
Pin No. 1 2 3 4 5,7,11,15,19,21, 26,31,33,37,39 6,10,12,16,18,20, 25,28,32,34,38 45, 55 44, 56 8 9 13 14 17 22 23 24 Mnemonic SYNC_IN SYNC_OUT MASTER_RESET PWR_DWN_CTL AVDD AGND DVDD DGND CH2_IOUT _________ CH2_IOUT CH3_IOUT _________ CH3_IOUT DAC_RSET OSC / REF_CLK OSC / REF_CLK CLK_MODE_SEL I/O I O I I I I I I O O O O I I I I
Preliminary Technical Data
Description Used to synchronize multiple AD9959s. Connect to the SYNC_OUT pin of the master AD9959. Used to synchronize multiple AD9959s. Connect to the SYNC_IN pin of the slave AD9959. Active high reset pin. Asserting the RESET pin forces the AD9959's internal registers to their default state, as described in the serial I/O port register map section in this document. External Power-Down Control. Analog Power Supply Pins (1.8V). Analog Ground Pins. Digital Power Supply Pins (1.8 V). Digital Power Ground Pins. True DAC Output. Terminate into AVDD. Complementary DAC Output. Terminate into AVDD. True DAC Output. Terminate into AVDD. Complementary DAC Output. Terminate into AVDD. Establishes the reference current for all DACs. A 1.962 k resistor (nominal) is connected from pin 17 to AGND. Complementary Reference Clock/Oscillator Input. When the REF_CLK is operated in singleended mode, this pin should be decoupled to AVDD or AGND with a 0.1 F capacitor. Reference Clock/Oscillator Input. When the REF_CLK is operated in single-ended mode, this is the input. Control Pin for the Oscillator Section. When high (1.8V), the oscillator section is enabled to accept a crystal as the REFCLK source. When low, the oscillator section is bypassed. CAUTION: Do not drive this pin beyond 1.8V. Connect to the external zero compensation network of the PLL loop filter for the REFCLK multiplier. For a 20x multiplier value the network should be a 1.2k resistor in series with a 1.2 nF capacitor tied to AVDD. Complementary DAC Output. Terminate into AVDD. True DAC Output. Terminate into AVDD. Complementary DAC Output. Terminate into AVDD. True DAC Output. Terminate into AVDD. These Pins are synchronous to the SYNC_CLK (pin 54). Any change in Profile inputs transfers the contents of the internal buffer memory to the I/O active registers (same as an external I/O _UPDATE). A rising edge detected on this pin transfers data from serial port buffer to active registers. Active low chip select allowing multiple devices to share a common I/O bus (SPI). Serial data clock for I/O operations. Data bits are written on rising edge of SCLK and read on the falling edge of SCLK. 3.3 V Digital Power Supply for SPI port and I/O (excluding CLK_MODE_SEL). These data pins have multiple functions. Data I/O pins for the serial I/O port operation. They are also used as data pins in modulation modes. I/O_UPDATE and Profile signals should meet the set-up and hold requirements with respect to this signal in order to guarantee a fixed pipeline delay of data to DAC outputs.
27
LOOP_FILTER
I
29 30 35 36 40, 41, 42, 43 46 47 48 49 50, 51 52, 53 54
_________ CH0_IOUT CH0_IOUT _________ CH1_IOUT CH1_IOUT PS0, PS1, PS2, PS3 I/O_UPDATE CS SCLK DVDD_I/O SDIO_0, SDIO_1 SDIO_2, SDIO_3 SYNC_CLK
O O O O I
I I I I I/O O
Rev. PrB | Page 8 of 9
Preliminary Technical Data
AD9959
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrB | Page 9 of 9
PR05246-0-11/04(PrB)

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